(1) Field of the Invention
The invention relates to a buck converting controller, and more particularly relates to a buck converting controller with preventing the overshoot.
(2) Description of the Prior Art
Relative to a fixed-frequency control structure, a constant on-time control structure applied to a DC-DC buck converting circuit greatly improves an undershoot of an output voltage. However, an overshoot of the output voltage does not be obviously improved.
FIG. 1 is a schematic diagram of a DC-DC buck converting circuit with inhibiting the overshoot disclosed in U.S. Pat. No. 7,274,177. Driving circuits 208 and 210 of a buck pulse width modulation stage respectively output a high-side control signal UG and a low-side control signal LG for respectively controlling a pair of power switches SW1 and SW2. The power switches SW1 and SW2 are, connected in series, between an input voltage Vin and a grounding for generating an inductance current IL by through an inductance L. A capacitance Co is charged through the inductance current IL to generate an output voltage Vout for a load 212. An overshoot inhibiting circuit 400 is coupled to the output voltage Vout and the grounding and comprises an inductance 412 and a transistor 414. An operation amplifier 416 serves as a voltage detector to detect the output voltage Vout and compares the output voltage Vout with a reference voltage Vref to generate a signal P1 for switching the transistor 414. The transistor 414 is cut off in normal state. When the output voltage Vout is higher than the reference voltage Vref, the signal P1 turns on the transistor 414. A diode D is coupled between the inductance 412 and a battery 418. If the capacitance Co is not enough to absorb the energy released by the inductance L, the output voltage Vout will exceed the reference voltage Vref when the load 212 changes from a heavy load to a light load. This causes the operation amplifier 416 to output the signal P1 to turn on the transistor 414. After the transistor 414 is turned on, the inductance 412 absorbs the energy released from the inductance L, and so pulls the output voltage Vout lower. Until the output voltage Vout is reduced to be lower than the reference voltage Vref, the operation amplifier 416 cuts off the transistor 414. Most of the released energy due to the changing of the load 212 is transmitted through the inductance 412 and the diode D into the battery 418 for storing. The battery 418 can supply power to other elements, and this system has almost no extra energy consumption.
FIG. 2 is a schematic diagram of a voltage-mode DC-DC buck converting circuit disclosed in U.S. Pat. No. 8,330,442. The voltage-mode DC-DC buck converting circuit comprises a control circuit 610, a gate driver circuit 620 and a power stage circuit 630. The control circuit 610 comprises an error amplifier 612, a modulator 614, a signal generator 616 and a comparator 618. The error amplifier 612 compares an output voltage Vout with a reference voltage Vref to generate a compensation signal Sc to the modulator 614. Besides, the signal generator 616 can output a ramp signal Sr with one of a first frequency F1 or a second frequency F2 to the modulator 614. The modulator 614 generates a PWM signal Sp according to the compensation signal Sc and the ramp signal Sr. The gate driver circuit 620 receives the PWM signal Sp and accordingly generates a first driving signal S1d and a second driving signal S2d to the power stage circuit 630. So, the power stage circuit 630 provides an output current Iout and the output voltage Vout.
The signal generator 616 can output the ramp signal Sr with the first frequency F1 or the second frequency F2, or other waveform signal with the first frequency F1 or the second frequency F2, such as: triangle wave signal. Wherein, the first frequency F1 is lower than the second frequency F2. Besides, the comparator 618 receives a threshold voltage Vth and the output voltage Vout. When the output voltage Vout is lower than the threshold voltage Vth, the comparator 618 outputs a first level signal to the signal generator 616. At this moment, the signal generator 616 outputs the ramp signal Sr with the first frequency F1 to the modulator 614. On the other hand, when the output voltage Vout is higher than the threshold voltage Vth, the comparator 618 outputs a second level signal to the signal generator 616. At this moment, the signal generator 616 outputs the ramp signal Sr with the second frequency F2 to the modulator 614.
When the compensation signal Sc is higher than the ramp signal Sr, the PWM signal Sp is at a high level. When the compensation signal Sc is lower than the ramp signal Sr, the PWM signal Sp is at a low level. Obviously, when the ramp signal Sr changes, the PWM signal Sp changes. Besides, when the ramp signal Sr is at the first frequency F1, the PWM signal Sp operates at the first frequency F1; when the ramp signal Sr is at the second frequency F2, the PWM signal Sp operates at the second frequency F2. Thereby, when the output voltage Vout is higher than the threshold voltage Vth, that is, when the overshoot occurring, the operating frequency is increased to increase the switching speed of the power stage circuit 630 and then inhibits the overshoot.
The aforementioned technology of inhibiting the overshoot is to compare the output voltage with the reference voltage, and executes the inhibiting overshoot when the overshoot occurring. FIG. 3 is a waveform diagram of a conventional overshoot inhibiting technology by comparing an output voltage with a reference voltage. At a time point t0, the output voltage Vout is higher than the threshold voltage Vth. However, since the circuit has time delays, the overshoot inhibiting postpones to execute at the time point t1. Therefore, the time delays in circuit are unfavorable to inhibit the overshoot. Furthermore, if the reference voltage is set too close to the expected output voltage, it affects the feedback control to make the feedback control be unsteady, but if the reference voltage is set farther, the effect of the overshoot inhibiting is very poor.